When a particular application/project/job requires more processing power than a single processor is capable of providing, it becomes necessary to provide a co-processor, such as a digital signal processor (DSP) or a floating point unit (FPU). Thus, the tasks associated with the particular application are handled in unison by the main processor and the co-processor. The most common conventional solution to solving the problem of how to allocate the resources to the multiple processors is to utilize a dual-ported memory subsystem wherein each processor has equal access to the common resources that may be used by both processors. Alternatively, each processor may be provided with a dedicated resource and a mechanism for transferring commands and data through a shared “Mail Box.” The shared “Mail Box” typically includes a number of first in/first out (FIFO) registers of varying length.
The conventional dual-ported memory solution provides processor independent design implementation, but requires a large amount of hardware for the random access arbitration for both processors. Consequently, the actual implementation of the arbitration logic and the random access for the common bus creates more delay on the common resources since the access to the common bus must be determined prior to accessing the common resources. The typically small degradation in the access speed in the dual-ported memory is magnified by a significant amount when that common resource is the main memory because the main memory is the common resource most utilized by both processors. Therefore, the interdependency of the multiple processors increases since they both rely heavily on the main memory.
The conventional dedicated resource for each processor with the share “Mail Box” scheme prevents the multiple processors from competing with each other for e same resource, but suffers greatly in terms of access speed both since the data and commands must all pass through the “Mail Box” which has a relatively narrow bandwidth. In addition duplicative resources are necessary since each processor has its own dedicated and duplicated resources. Although the scheme works quite well when the tasks for the processors are well defined and common mailbox data transfer size is relatively small, the actual performance resource utilization suffers greatly when the tasks are not well defined and the processors are therefore more interdependent. Thus, there is a need in the art for a system and method which permits multiple processors to communicate with each other and control the access to the shared resources.
Although multiprocessors enhance the performance of a computer system, the multiple processors also create additional problems, such as when more than one of the processors attempts to access a shared hardware or software resource at the same time. A conventional solution to this problem has been through the use of semaphores located in memory. In general, semaphores are counters that are used to control access to shared resources by multiple processes. Semaphores are commonly used as a locking mechanism to prevent processes from accessing a particular resource while another process is performing operations on it. In operation, for example, if a processor wants to access a system resource it must first check the status of the desired resource by sending a read command over the system bus to the associated semaphore in the system memory, and the semaphore returns the status information back to the processor. If the desired resource is available, the processor sends a write command to the semaphore to change the status of the semaphore from “available” to “unavailable.” To prevent another process or processor from checking the status of the semaphore concurrent with the processor, prior to sending the read command, the processor will traditionally lock the system bus until the read/write routine is completed. Not only does locking the system bus prevent another processor or “master” from accessing the particular semaphore, but it also prevents the other processors from communicating with the other devices on the bus. This is disadvantageous in that it slows the efficiency of the system, resulting in an increased latency of system operations which defeats the advantages of utilizing a multiple processor architecture.
Accordingly, there is a need in the art for a system and method that permits multiple processors to communicate with each other and to control access to shared resources without “locking” the system bus, thus maintaining the increased efficiency and additional advantages offered by a multiprocessor system. It is to this end that the present invention is directed.